Silicon Motion unveils the SM2524XT PCIe Gen 5 SSD controller without DRAM

Hardware specifications and throughput

The SM2524XT is manufactured on TSMC's 6nm process and utilizes a four-core architecture. Utilizing PCIe Gen 5 x4 and NAND interface speeds of up to 4,800 MT/s, the controller achieves sequential read speeds of up to 14 GB/s. In the area of random I/O, the device achieves up to 2.5 million IOPS.

Compared to the previous generation of controllers, the SM2524XT offers 25 percent higher performance per watt. It also delivers up to 25 percent improvement in random performance, which directly reduces latency in the fragmented data access patterns typical of AI workloads.

With the proliferation of on-device AI, the KV cache has become a primary bottleneck for system responsiveness. Unlike standard consumer SSD tasks, KV cache operations involve continuous streams of fragmented, latency-sensitive random reads and writes.

The SM2524XT is designed to maintain stable random I/O throughput and low latency performance even under heavy, sustained load. This makes it a critical component for AI PCs supporting complex on-device LLMs and local agents that require consistent data access to avoid performance degradation.

Technologies for parallel processing and stability

To ensure consistent performance during intensive AI sessions, Silicon Motion has integrated several proprietary technologies into the SM2524XT:

• Separated Command Address (SCA): Improves parallel data processing efficiency.
• Advanced FTL Scheduling: Optimizes management and access to data in NAND flash.
• NANDXtend LDPC ECC**: Improves error correction to reduce latency interruptions.

These combined features enable the controller to maintain high throughput and stability in environments with thermal and power constraints, ensuring that the storage layer does not impact the overall speed of AI inference.