Computer Forum
Core Ultra 300 CPUs (Image © TechPowerUp)
Core Ultra 5 400S Core Configuration and Thermal Design
The upcoming processors will feature a 22-core layout consisting of six Coyote Cove P-cores for heavy workloads, twelve Arctic Wolf E-cores for efficiency, and four LPE cores for low-power tasks. These are integrated into a single computing chip. Intel plans two main versions of this configuration: an unlocked model with a TDP of 125 W, designed for overclocking enthusiasts, and a standard version limited to a base TDP of 65 W.
Impact of the Large Last-Level Cache (bLLC)
To compete more effectively in the gaming sector, Intel is implementing a 108 MB large last-level cache (bLLC). This architectural shift mirrors strategies employed by competitors to improve performance in latency-sensitive applications. By increasing the amount of data stored closer to the CPU cores, Intel aims to improve frame rates and overall responsiveness in modern games.
New Socket and Platform Infrastructure
The Nova Lake-S CPUs will transition to the LGA-1954 socket on the Z9x0 platform. Due to the high pin count—nearly 2,000 pins—Intel has introduced an independent loading mechanism (ILM) with two levers. This mechanical change is necessary to ensure stable contact and even pressure across the larger CPU packages. The new platform is designed for significant scalability; according to reports, it can accommodate up to 52 cores in a single socket. This brings workstation-level core densities to the consumer market. However, this performance boost comes with higher power requirements; rumors suggest that some configurations have a PL2 power consumption of up to 474 W.
Core Ultra 5 400S Launch
The first wave of Nova Lake-S processors is expected to hit the market in a few months, marking a significant shift in Intel’s approach to consumer gaming hardware and platform stability.
