Computer Forum
[page “Diamond Rapids Xeon 7”]
Intel Clearwater Forest CPU (Image © Intel/Tencent)
The Diamond Rapids Xeon 7 utilizes the Panther Cove-X architecture and supports a maximum configuration of 256 P-cores. Unlike earlier versions, which relied on Simultaneous Multithreading, this architecture features 256 threads in the 256-core variant. The memory and cache specifications are designed for high-density cloud workloads. The processor features a shared 1.28 GB last-level cache (LLC), with 320 MB allocated per base tile. The memory subsystem consists of 16 channels that support RDIMM speeds of up to 8,000 MT/s and MRDIMM speeds of up to 12,800 MT/s, delivering a maximum memory bandwidth of 1.6 TB/s via a unified memory architecture.
Intel Diamond Rapids HotChips 26 (Image © Intel/Tencent)
Manufacturing Process and Physical Integration
This CPU marks the first use of 18A-P process technology for Intel data center products. The chip utilizes a disaggregated tile design:
- Compute tiles: Manufactured using the 18A-P node.
- I/O tile: Manufactured using the Intel 3 process.
These components are integrated via Foveros Direct 3D hybrid bonding. To accommodate the increased heat dissipation with a maximum TDP of 650 W, Intel has introduced a new heat spreader and a redesigned pin layout. The processor will use the LGA-9324 socket, known as “Oak Stream.”
AI Acceleration and Connectivity
The Xeon 7 was designed for AI infrastructures and integrates AMX and AVX-10.2 extensions to optimize token processing and inference performance. These extensions enable the CPU to process smaller AI large language models (LLMs) with efficiency approaching that of discrete GPUs by utilizing unused CPU resources. In terms of connectivity, the platform offers 128 PCIe Gen 6 lanes and supports CXL 3.0, ensuring high-speed communication between the CPU, accelerators, and memory arrays.
Xeon 7 Specifications vs. EPYC
The Diamond Rapids product line is entering a market already dominated by AMD’s EPYC 9006 Venice series. The Venice CPUs, based on the Zen 6 architecture, are scheduled to launch in 2026, preceding the Xeon 7. A technical comparison yields the following specifications:
| Feature Overview | Intel Diamond Rapids vs. AMD EPYC Venice |
|---|---|
| Max. Cores | Intel Diamond Rapids: 256 P-cores (Panther Cove-X) AMD EPYC Venice: 256 (Zen 6C) / 96 (Zen 6) |
| Max. Threads | Intel Diamond Rapids: 256 AMD EPYC Venice: 512 (Zen 6C) / 192 (Zen 6) |
| L3 Cache | Intel Diamond Rapids: 1.28 GB AMD EPYC Venice: 1024 MB (Zen 6C) / 384 MB (Zen 6) |
| Memory channels | Intel Diamond Rapids: 16 AMD EPYC Venice: 16 (SP7) / 8 (SP8) |
| Maximum memory speed | Intel Diamond Rapids: 12,800 MT/s (MRDIMM) AMD EPYC Venice: 12,800 MT/s (MRDIMM) |
| Processing nodes | Intel Diamond Rapids: 18A-P (Compute) / Intel 3 (IO) AMD EPYC Venice: N2/N2P (Compute) / N3 (IO) |
| Socket | Intel Diamond Rapids: LGA 9324 AMD EPYC Venice: SP7 / SP8 |
| Max. TDP | Intel Diamond Rapids: 650 W AMD EPYC Venice: 600 W (SP7) |
| PCIe Version | Intel Diamond Rapids: Gen6 + CXL 3.0 AMD EPYC Venice: Gen6 + CXL 3.1 |
| Expected Market Launch | Intel Diamond Rapids: 2027 AMD EPYC Venice: 2026 |
Internal forecasts suggest that Intel may not achieve full performance parity with AMD’s high-end products until the release of the Coral Rapids product line in 2028.
Intel Xeon 6 Slides (Image © Intel/Tencent)
The presentation took place alongside announcements regarding the latest upgrades to Tencent’s cloud infrastructure. Tencent is migrating its Cloud Virtual Machines (CVM) from Granite Rapids AP Xeon 6 to Clearwater Forest AP Xeon 6+.
Data from these deployments shows that the Xeon 6+ Clearwater Forest CPUs support over 350 concurrent sandboxes with an average creation latency of 200 ms, representing a 1.46-fold performance increase over previous test platforms. This infrastructure currently supports the deployment of over 100,000 sandboxes within a few minutes. Furthermore, AMX acceleration in these latest chips has demonstrated a 1.3- to 3.4-fold improvement in inference performance compared to conventional AVX-512.
