AMD EPYC 9006 SP7/SP8 Venice: 2-nm Server CPUs, Specifications, and Full Details

2-nm Process and Chiplet Layout

The EPYC 9006 Venice Series are the first high-performance computing chips to enter mass production using TSMC’s 2-nm node. While the compute chiplets (CCDs) use the 2-nm process, the I/O dies are manufactured using the 6-nm process. This transition enables a 10–15% increase in performance at the same power consumption, as well as a 25–30% reduction in power consumption at constant performance.

The flagship configuration includes approximately 203 billion transistors. AMD has redesigned the CCD layout; each high-density Zen 6c CCD now features 32 cores and 128 MB of L3 cache. By arranging eight of these CCDs on a single package, the top-of-the-line EPYC 9996 model achieves 256 cores and 512 threads, as well as a total of 1,024 MB of L3 cache per socket. Models with higher clock speeds use standard Zen 6 CCDs. These scale up to 128 cores and 256 threads, with the EPYC 9686F variant designed for clock speeds of up to 5.0 GHz.

Dual-I/O-Die Architecture and Memory Bandwidth

A significant architectural change in the Venice series is the shift from a single I/O die (IOD) to a dual-IOD design. This modification expands the data pipeline to support 16 DDR5 memory channels—an increase over the 12 channels of the previous Turin generation. The dual-IOD configuration enables memory bandwidth of up to 1.6 TB/s per socket. This is supported by standard DDR5 RDIMMs running at 8,000 MT/s or second-generation MRDIMMs running at 12,800 MT/s.

In terms of connectivity, Venice introduces PCIe Gen 6. Single-socket configurations offer 128 lanes, while dual-socket configurations provide up to 160 lanes. Although current GPUs typically operate on PCIe Gen 5, the Gen 6 host provides more lanes overall for networking, memory, and future hardware.

SP7 Socket, Models, and Prices

AMD has unveiled nine SKUs for the SP7 platform. The prices and number of cores are as follows:

• EPYC 9996: 256 cores, 512 threads, 4.1 GHz boost, 1,024 MB L3, 600 W, MSRP $14,904
• EPYC 9966: 192 cores, 384 threads, 4.0 GHz boost, 768 MB L3, 600 W, MSRP $14,079
• EPYC 9846:

168 cores, 336 threads, 3.7 GHz boost, 768 MB L3, 500 W, MSRP $13,114 - EPYC 9756: 128 cores, 256 threads, 4.0 GHz boost, 512 MB L3, 500 W, MSRP $12,498 - EPYC 9G76: 96 cores, 192 threads, 4.8 GHz boost, 384 MB L3, 500 W, MSRP $11,622 - EPYC 9686F: 96 cores, 192 threads, 5.0 GHz boost, 384 MB L3, 500 W, MSRP $11,434 - EPYC 9656: 96 cores, 192 threads, 3.7 GHz boost, 512 MB L3, 400 W, MSRP $9,713 - EPYC 9586F: 64 cores, 128 threads, 5.0 GHz boost, 384 MB L3, 500 W, MSRP $9,701 - EPYC 9556: 64 cores, 128 threads, 4.3 GHz boost, 384 MB L3, 300 W, MSRP $8,008

Platform Variants and Availability

The Zen 6 architecture is divided into four different platform configurations:

• 1. EPYC 9006 SP7: The flagship among high-density options for running agents and as a GPU host.
• 2. EPYC 9006X SP7: A version that utilizes 3D V-Cache to triple the L3 cache per core and is geared toward HPC and simulation.
• 3. EPYC 9006 LP: Designed as an AI host node with 24-channel LPDDR5X via SOCAMM2 modules, supporting up to 72 cores.
• 4. EPYC 9006 SP8: A mainstream platform featuring the LGA-5572 socket, 8 to 128 cores, and 8-channel DDR5.

Shipments will begin in the fourth quarter of 2026 with the SP7. The SP8 platform is scheduled for the first half of 2027, while the 9006X and LP variants will launch in the second half of 2027.

Thermal Requirements and Power Consumption

The top-of-the-line EPYC 9996 has a TDP of 600 W. In a densely packed 4U chassis with eight GPUs, the total heat dissipation can exceed 6 kW per rack unit. Due to this power density, liquid cooling is required to prevent thermal throttling and maintain consistent performance under load.

Workload Optimization

AMD has divided the Venice architecture into three functional roles:

• Agent Sandbox: SP7 units with a high core count handle the parallelism and memory state required to coordinate multiple autonomous agents.
• AI Host Node: High-frequency variants and LP configurations leverage PCIe Gen 6 and high memory bandwidth to prevent a GPU bottleneck.

• General Purpose: The SP8 platform targets database and application services where per-core licensing efficiency is more important than peak throughput.