Computer Forum
Intel D270 KI Beschleuniger (Image © Intel)
The D-Series accelerator is based on 32 Xe3P cores and 256 XMX engines. A key technical feature of the Xe3P architecture is the redesign of the XMX engine pipeline. While the standard Xe3 uses a four-level systolic design, the Xe3P implements 16-level processing, which significantly changes the way data is processed within the engine.
The core distribution is organized into 256 vector engines and 256 XMX engines, grouped in sets of eight per Xe3P core. To support high-performance computing, on-chip memory is integrated:
- Unified L2 cache: 32 MB.
- L1 cache: 512 KB per core.
- Register files: 1 MB per core.
Memory Configurations and VRAM Capacity
The D-series offers several memory options using LPDDR5X memory. The standard configuration provided by Intel for “Crescent Island” cards is 160 GB. However, ODMs can also increase this capacity, and Intel supports up to 480 GB of LPDDR5X memory. This high VRAM capacity is intended to facilitate the loading of large language models and complex AI datasets.
Performance of the New D-GPUs
In terms of raw performance, the D-Series is designed for FP8 performance of up to 1.3 petaFLOPS. The cards offer comprehensive compatibility with various data formats ranging from FP4 to FP64. In addition, the accelerator features a dedicated media engine with four encoders and four decoders. This hardware addition was developed to support multimodal AI workloads, particularly those requiring the simultaneous generation and understanding of video content.
Intel uses PCIe 5.0 x16 as the interface, and the thermal design power (TDP) is 350 W. To ensure compatibility with conventional server chassis, the card uses air cooling, eliminating the need for specialized liquid cooling systems.
On the software side, Intel uses its unified Xe software platform and ensures compatibility with established AI frameworks to simplify deployment for enterprise customers.
However, Intel did not specify a price in the press release.
